On-Chip Networks

On-Chip Networks

Li-Shiuan Peh, Natalie Enright Jerger
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With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field. Table of Contents: Introduction / Interface with System Architecture / Topology / Routing / Flow Control / Router Microarchitecture / Conclusions
年:
2009
版本:
1
出版商:
Morgan and Claypool Publishers
語言:
english
頁數:
141
ISBN 10:
1598295845
ISBN 13:
9781598295849
系列:
Synthesis Lectures on Computer Architecture
文件:
PDF, 2.41 MB
IPFS:
CID , CID Blake2b
english, 2009
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